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integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion 

CPUs with a dedicated memory port (MemBus) are typically connected
directly to the LiteDRAM port. Some models (e.g., Rocket) come in
(otherwise equivalent) variants specifically pre-generated to fit
the various "standard" LiteDRAM port widths (so far, 64, 128, or
256 bits).

This patch introduces a warning when the CPU variant's dedicated
MemBus doesn't exactly match the width of LiteDRAM, requiring
explicit conversion.

The goal is to inform the user and provide them with an opportunity
to pick a more suitable CPU variant (of matching MemBus width), if
available.
This commit is contained in:
Gabriel Somlo 2022-12-02 10:32:35 -05:00
parent fe7e70baa9
commit be40e796f2
1 changed files with 4 additions and 0 deletions
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4
litex/soc/integration/soc.py
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@ -1529,6 +1529,10 @@ class LiteXSoC(SoC):
# Check if bus is an AXI bus and connect it. # Check if bus is an AXI bus and connect it.
if isinstance(mem_bus, axi.AXIInterface): if isinstance(mem_bus, axi.AXIInterface):
data_width_ratio = int(port.data_width/mem_bus.data_width) data_width_ratio = int(port.data_width/mem_bus.data_width)
if data_width_ratio != 1:
self.logger.warning("Converting MemBus({}) data width to LiteDRAM({}).".format(
colorer(mem_bus.data_width, color="yellow"),
colorer(port.data_width, color="yellow")))
# If same data_width, connect it directly. # If same data_width, connect it directly.
if data_width_ratio == 1: if data_width_ratio == 1:
self.submodules += LiteDRAMAXI2Native( self.submodules += LiteDRAMAXI2Native(