integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion
CPUs with a dedicated memory port (MemBus) are typically connected directly to the LiteDRAM port. Some models (e.g., Rocket) come in (otherwise equivalent) variants specifically pre-generated to fit the various "standard" LiteDRAM port widths (so far, 64, 128, or 256 bits). This patch introduces a warning when the CPU variant's dedicated MemBus doesn't exactly match the width of LiteDRAM, requiring explicit conversion. The goal is to inform the user and provide them with an opportunity to pick a more suitable CPU variant (of matching MemBus width), if available.
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@ -1529,6 +1529,10 @@ class LiteXSoC(SoC):
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# Check if bus is an AXI bus and connect it.
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# Check if bus is an AXI bus and connect it.
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if isinstance(mem_bus, axi.AXIInterface):
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if isinstance(mem_bus, axi.AXIInterface):
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data_width_ratio = int(port.data_width/mem_bus.data_width)
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data_width_ratio = int(port.data_width/mem_bus.data_width)
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if data_width_ratio != 1:
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self.logger.warning("Converting MemBus({}) data width to LiteDRAM({}).".format(
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colorer(mem_bus.data_width, color="yellow"),
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colorer(port.data_width, color="yellow")))
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# If same data_width, connect it directly.
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# If same data_width, connect it directly.
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if data_width_ratio == 1:
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if data_width_ratio == 1:
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self.submodules += LiteDRAMAXI2Native(
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self.submodules += LiteDRAMAXI2Native(
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