Merge pull request #774 from antmicro/vex-debug
CPU: Vex: add debug slave for dbg cpu variant
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bf0f0176b3
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@ -265,6 +265,11 @@ class VexRiscv(CPU, AutoCSR):
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vdir = get_data_mod("cpu", "vexriscv").data_location
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vdir = get_data_mod("cpu", "vexriscv").data_location
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platform.add_source(os.path.join(vdir, cpu_filename))
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platform.add_source(os.path.join(vdir, cpu_filename))
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def add_soc_components(self, soc, soc_region_cls):
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if "debug" in self.variant:
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soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(origin=0xf00f0000, size=0x100, cached=False))
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def use_external_variant(self, variant_filename):
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def use_external_variant(self, variant_filename):
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self.external_variant = True
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self.external_variant = True
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self.platform.add_source(variant_filename)
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self.platform.add_source(variant_filename)
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