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fix vexriscv build

This commit is contained in:
Kurt Kiefer 2019-04-27 14:57:35 -07:00 committed by Florent Kermarrec
parent 2d5bae3def
commit bf27869ad9
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/cpu/vexriscv/core.py
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@ -49,7 +49,7 @@ class VexRiscv(Module, AutoCSR):
def __init__(self, platform, cpu_reset_address, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.gcc_flags = GCC_FLAGS[variant]
self.gcc_flags = GCC_FLAGS[variant] + " -D__vexriscv__"
self.platform = platform
self.variant = variant
@ -184,7 +184,7 @@ class VexRiscv(Module, AutoCSR):
@staticmethod
def add_sources(platform, variant="standard"):
cpu_filename = CPU_VARIANTS[variant]
cpu_filename = CPU_VARIANTS[variant] + ".v"
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, cpu_filename))