Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

bus/dfi: filter signals by direction

This commit is contained in:
Sebastien Bourdeauducq 2012-02-15 21:48:05 +01:00
parent ef7aea0f31
commit c08687b9c6
1 changed files with 9 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
migen/bus/dfi.py
View File

@ -26,19 +26,20 @@ class Interface:
self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
# Returns pairs (DFI-mandated signal name, Migen signal object)
def get_standard_names(self):
def get_standard_names(self, m2s=True, s2m=True):
r = []
add_suffix = len(self.phases) > 1
for n, phase in enumerate(self.phases):
for signal in self.pdesc.desc:
if add_suffix:
if signal[0] == M_TO_S:
suffix = "_p" + int(n)
if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
if add_suffix:
if signal[0] == M_TO_S:
suffix = "_p" + int(n)
else:
suffix = "_w" + int(n)
else:
suffix = "_w" + int(n)
else:
suffix = ""
r.append(("dfi_" + signal[1] + suffix, getattr(self, signal[1])))
suffix = ""
r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))
return r
class Interconnect: