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bus/dfi: filter signals by direction
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parent
ef7aea0f31
commit
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1 changed files with 9 additions and 8 deletions
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@ -26,11 +26,12 @@ class Interface:
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self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
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self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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def get_standard_names(self):
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def get_standard_names(self, m2s=True, s2m=True):
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r = []
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r = []
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add_suffix = len(self.phases) > 1
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add_suffix = len(self.phases) > 1
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for n, phase in enumerate(self.phases):
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for n, phase in enumerate(self.phases):
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for signal in self.pdesc.desc:
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for signal in self.pdesc.desc:
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if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
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if add_suffix:
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if add_suffix:
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if signal[0] == M_TO_S:
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if signal[0] == M_TO_S:
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suffix = "_p" + int(n)
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suffix = "_p" + int(n)
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@ -38,7 +39,7 @@ class Interface:
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suffix = "_w" + int(n)
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suffix = "_w" + int(n)
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else:
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else:
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suffix = ""
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suffix = ""
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r.append(("dfi_" + signal[1] + suffix, getattr(self, signal[1])))
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r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))
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return r
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return r
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class Interconnect:
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class Interconnect:
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