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soc/cores/hyperbus: Minor cleanups.

This commit is contained in:
Florent Kermarrec 2024-08-22 17:36:47 +02:00
parent 3213cf8f84
commit c09d57d52d
1 changed files with 5 additions and 4 deletions
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9
litex/soc/cores/hyperbus.py
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@ -210,9 +210,7 @@ class HyperRAM(LiteXModule):
self.sync += If(phy.shift, shift_reg_data.eq(shift_reg_data_next)) self.sync += If(phy.shift, shift_reg_data.eq(shift_reg_data_next))
# Load. # Load.
self.sync += If(shift_reg_load, self.sync += If(shift_reg_load, shift_reg_data.eq(shift_reg_load_data))
shift_reg_data.eq(shift_reg_load_data)
)
# Register Access/Buffer ------------------------------------------------------------------- # Register Access/Buffer -------------------------------------------------------------------
reg_wr_req = Signal() reg_wr_req = Signal()
@ -259,7 +257,9 @@ class HyperRAM(LiteXModule):
) )
] ]
# Bus Latch -------------------------------------------------------------------------------- # Bus Latch/Output -------------------------------------------------------------------------
# Latch.
bus_adr = Signal(32) bus_adr = Signal(32)
bus_we = Signal() bus_we = Signal()
bus_sel = Signal(4) bus_sel = Signal(4)
@ -273,6 +273,7 @@ class HyperRAM(LiteXModule):
shift_reg_load.eq(1), shift_reg_load.eq(1),
shift_reg_load_data.eq(Cat(Signal(16), bus.dat_w)), shift_reg_load_data.eq(Cat(Signal(16), bus.dat_w)),
) )
# Output.
self.comb += bus.dat_r.eq(shift_reg_data_next) self.comb += bus.dat_r.eq(shift_reg_data_next)
# FSM (Sequencer) -------------------------------------------------------------------------- # FSM (Sequencer) --------------------------------------------------------------------------