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specials/Memory: allow for more flexibility in memory port signals

This commit is contained in:
Sebastien Bourdeauducq 2013-12-12 17:36:17 +01:00
parent 135a4fea25
commit c13fe1bc63
1 changed files with 9 additions and 2 deletions
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9
migen/fhdl/specials.py
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@ -177,7 +177,10 @@ class _MemoryPort(Special):
self.re = re self.re = re
self.we_granularity = we_granularity self.we_granularity = we_granularity
self.mode = mode self.mode = mode
if isinstance(clock_domain, str):
self.clock = ClockSignal(clock_domain) self.clock = ClockSignal(clock_domain)
else:
self.clock = clock_domain
def iter_expressions(self): def iter_expressions(self):
for attr, target_context in [ for attr, target_context in [
@ -231,7 +234,11 @@ class Memory(Special):
@staticmethod @staticmethod
def emit_verilog(memory, ns): def emit_verilog(memory, ns):
r = "" r = ""
gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals def gn(e):
if isinstance(e, Memory):
return ns.get_name(e)
else:
return verilog_printexpr(ns, e)[0]
adrbits = bits_for(memory.depth-1) adrbits = bits_for(memory.depth-1)
r += "reg [" + str(memory.width-1) + ":0] " \ r += "reg [" + str(memory.width-1) + ":0] " \