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soc/integration/soc: add_jtagbone: pass address_width to UARTBone constructor

This commit is contained in:
Gwenhael Goavec-Merou 2023-12-09 06:07:58 +01:00
parent acd66f1346
commit c1871eaf42
1 changed files with 5 additions and 1 deletions
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6
litex/soc/integration/soc.py
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@ -1527,7 +1527,11 @@ class LiteXSoC(SoC):
# Core.
self.check_if_exists(name)
jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain, platform=self.platform)
jtagbone = uart.UARTBone(phy=jtagbone_phy, clk_freq=self.sys_clk_freq)
jtagbone = uart.UARTBone(
phy = jtagbone_phy,
clk_freq = self.sys_clk_freq,
address_width = self.bus.address_width
)
self.add_module(name=f"{name}_phy", module=jtagbone_phy)
self.add_module(name=name, module=jtagbone)
self.bus.add_master(name=name, master=jtagbone.wishbone)