Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware

This commit is contained in:
Florent Kermarrec 2017-11-24 13:16:58 +01:00
parent 831b489fd3
commit c1eba9a6cc
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/soc/integration/soc_core.py
View File

@ -64,7 +64,7 @@ class SoCCore(Module):
cpu_type="lm32", cpu_reset_address=0x00000000, cpu_type="lm32", cpu_reset_address=0x00000000,
integrated_rom_size=0, integrated_rom_size=0,
integrated_sram_size=4096, integrated_sram_size=4096,
integrated_main_ram_size=0, integrated_main_ram_size=0, integrated_main_ram_init=[],
shadow_base=0x80000000, shadow_base=0x80000000,
csr_data_width=8, csr_address_width=14, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200, uart_stub=False, with_uart=True, uart_baudrate=115200, uart_stub=False,
@ -123,7 +123,7 @@ class SoCCore(Module):
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size: if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size) self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR( self.submodules.wishbone2csr = wishbone2csr.WB2CSR(