Merge pull request #1309 from jevinskie/jev/bug/intel-clocking-indent

Intel Clocking: compute_config() fix indent causing PLL config error
2022-05-24 09:31:54 +02:00 · 2022-05-24 09:31:54 +02:00 · c2e9125d05
parent 6e42082128 68fe6a30fd
commit c2e9125d05
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/cores/clock/intel_common.py
+++ b/litex/soc/cores/clock/intel_common.py
@ -70,8 +70,8 @@ class IntelClocking(Module, AutoCSR):
                                break
                            if valid:
                                break
-                    if not valid:
+                        if not valid:
-                        all_valid = False
+                            all_valid = False
                else:
                    all_valid = False
                if all_valid: