interconnect/stream: Revert Convert to Module, needs to be investigated.

2023-10-27 12:33:37 +02:00 · 2023-10-27 12:33:37 +02:00 · c44b906d9f
parent 856d7452b3
commit c44b906d9f
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@ -470,7 +470,7 @@ def _get_converter_ratio(nbits_from, nbits_to):
    return converter_cls, ratio


-class Converter(LiteXModule):
+class Converter(Module): # FIXME: Switch to LiteXModule.
    def __init__(self, nbits_from, nbits_to,
        reverse                  = False,
        report_valid_token_count = False):