targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.

2020-02-27 13:00:35 +01:00 · 2020-02-27 13:00:35 +01:00 · c4fd6a7f2f
parent 78a3223573
commit c4fd6a7f2f
1 changed files with 3 additions and 1 deletions
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@ -57,8 +57,10 @@ class BaseSoC(SoCSDRAM):
            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                memtype      = "DDR3",
                nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
            self.add_csr("ddrphy")
+            self.add_constant("DDRPHY_CMD_DELAY", 13)
            sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
            self.register_sdram(self.ddrphy,
                geom_settings   = sdram_module.geom_settings,