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soc/integration/soc/add_uart: Allow directly passing uart_pads. 

Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.
This commit is contained in:
Florent Kermarrec 2024-07-22 16:22:29 +02:00
parent b8cb6da2b9
commit c51d22074f
1 changed files with 4 additions and 3 deletions
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3
litex/soc/integration/soc.py
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@ -1512,7 +1512,7 @@ class LiteXSoC(SoC):
self.add_config(name, identifier) self.add_config(name, identifier)
# Add UART ------------------------------------------------------------------------------------- # Add UART -------------------------------------------------------------------------------------
def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16): def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16):
# Imports. # Imports.
from litex.soc.cores.uart import UART, UARTCrossover from litex.soc.cores.uart import UART, UARTCrossover
@ -1529,6 +1529,7 @@ class LiteXSoC(SoC):
"usb_acm", "usb_acm",
"serial(x)", "serial(x)",
] ]
if uart_pads is None:
uart_pads_name = "serial" if uart_name == "sim" else uart_name uart_pads_name = "serial" if uart_name == "sim" else uart_name
uart_pads = self.platform.request(uart_pads_name, loose=True) uart_pads = self.platform.request(uart_pads_name, loose=True)
uart_phy = None uart_phy = None