soc/integration/soc/add_uart: Allow directly passing uart_pads.

Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.

litex/soc/integration/soc.py

@@ -1512,7 +1512,7 @@ class LiteXSoC(SoC):
         self.add_config(name, identifier)
 
     # Add UART -------------------------------------------------------------------------------------
-    def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16):
+    def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16):
         # Imports.
         from litex.soc.cores.uart import UART, UARTCrossover
 
@@ -1529,6 +1529,7 @@ class LiteXSoC(SoC):
             "usb_acm",
             "serial(x)",
         ]
+        if uart_pads is None:
             uart_pads_name = "serial" if uart_name == "sim" else uart_name
             uart_pads      = self.platform.request(uart_pads_name, loose=True)
         uart_phy       = None