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misoclib/soc: add _integrated_ to cpu options to avoid confusion

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This commit is contained in:
Florent Kermarrec 2015-03-21 20:51:26 +01:00
parent b75e4b237d
commit c55199deb9
10 changed files with 28 additions and 28 deletions
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6
make.py
View file

@ -122,9 +122,9 @@ CPU type: {}
actions["build-bios"] = True
if not actions["load-bitstream"]:
actions["flash-bitstream"] = True
if not soc.with_rom:
if not soc.with_integrated_rom:
actions["flash-bios"] = True
if actions["build-bitstream"] and soc.with_rom:
if actions["build-bitstream"] and soc.with_integrated_rom:
actions["build-bios"] = True
if actions["build-bios"]:
actions["build-headers"] = True
@ -173,7 +173,7 @@ CPU type: {}
raise OSError("BIOS build failed")
if actions["build-bitstream"]:
if soc.with_rom:
if soc.with_integrated_rom:
with open(soc.cpu_boot_file, "rb") as boot_file:
boot_data = []
while True:

20
misoclib/soc/__init__.py
View file

@ -37,9 +37,9 @@ class SoC(Module):
def __init__(self, platform, clk_freq, cpu_or_bridge=None,
with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000,
cpu_boot_file="software/bios/bios.bin",
with_rom=False, rom_size=0x8000,
with_sram=True, sram_size=4096,
with_main_ram=False, main_ram_size=64*1024,
with_integrated_rom=False, rom_size=0x8000,
with_integrated_sram=True, sram_size=4096,
with_integrated_main_ram=False, main_ram_size=64*1024,
with_csr=True, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
with_identifier=True,
@ -50,19 +50,19 @@ class SoC(Module):
self.with_cpu = with_cpu
self.cpu_type = cpu_type
if with_rom:
if with_integrated_rom:
self.cpu_reset_address = 0
else:
self.cpu_reset_address = cpu_reset_address
self.cpu_boot_file = cpu_boot_file
self.with_rom = with_rom
self.with_integrated_rom = with_integrated_rom
self.rom_size = rom_size
self.with_sram = with_sram
self.with_integrated_sram = with_integrated_sram
self.sram_size = sram_size
self.with_main_ram = with_main_ram
self.with_integrated_main_ram = with_integrated_main_ram
self.main_ram_size = main_ram_size
self.with_uart = with_uart
@ -90,16 +90,16 @@ class SoC(Module):
self.cpu_or_bridge = self.cpu
self._wb_masters += [self.cpu.ibus, self.cpu.dbus]
if with_rom:
if with_integrated_rom:
self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
self.register_rom(self.rom.bus, rom_size)
if with_sram:
if with_integrated_sram:
self.submodules.sram = wishbone.SRAM(sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if with_main_ram:
if with_integrated_main_ram:
self.submodules.main_ram = wishbone.SRAM(main_ram_size)
self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size)

2
misoclib/soc/sdram.py
View file

@ -80,7 +80,7 @@ class SDRAMSoC(SoC):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
def do_finalize(self):
if not self.with_main_ram:
if not self.with_integrated_main_ram:
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self)

4
targets/de0nano.py
View file

@ -85,12 +85,12 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=100*1000000,
with_rom=True,
with_integrated_rom=True,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_module = IS42S16160(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,

4
targets/kc705.py
View file

@ -83,7 +83,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform)
if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_modules = MT8JTF12864(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@ -103,7 +103,7 @@ class BaseSoC(SDRAMSoC):
self.flash_boot_address = 0xb00000
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
if not self.with_integrated_rom:
self.register_rom(self.spiflash.bus)
class MiniSoC(BaseSoC):

4
targets/mlabs_video.py
View file

@ -41,7 +41,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_modules = MT46V32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@ -64,7 +64,7 @@ class BaseSoC(SDRAMSoC):
self.flash_boot_address = 0x001a0000
# If not in ROM, BIOS is in // NOR flash
if not self.with_rom:
if not self.with_integrated_rom:
self.register_rom(self.norflash.bus)

6
targets/pipistrello.py
View file

@ -91,14 +91,14 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, **kwargs):
clk_freq = 75*1000*1000
if not kwargs.get("with_rom"):
if not kwargs.get("with_integrated_rom"):
kwargs["rom_size"] = 0x1000000 # 128 Mb
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, **kwargs) # 1.5 MB
self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_module = MT46H32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@ -119,7 +119,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
if not self.with_integrated_rom:
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus)

4
targets/ppro.py
View file

@ -74,7 +74,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_module = MT48LC4M16(clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@ -89,7 +89,7 @@ class BaseSoC(SDRAMSoC):
self.flash_boot_address = 0x70000
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
if not self.with_integrated_rom:
self.register_rom(self.spiflash.bus)
default_subtarget = BaseSoC

4
targets/simple.py
View file

@ -10,8 +10,8 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
with_rom=True,
with_main_ram=True, main_ram_size=16*1024,
with_integrated_rom=True,
with_integrated_main_ram=True, main_ram_size=16*1024,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

2
targets/versa.py
View file

@ -9,7 +9,7 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=100*1000000,
with_rom=True,
with_integrated_rom=True,
**kwargs)
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
self.comb += platform.request("user_led", 0).eq(ResetSignal())