commit
c615b50735
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@ -17,7 +17,7 @@ class Core(Module):
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self.clk_freq = clk_freq
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# SATA PHY/Core/Frontend
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self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
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self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq)
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self.submodules.sata_core = LiteSATACore(self.sata_phy)
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self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
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@ -13,8 +13,7 @@ crc_tb:
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$(CC) $(CFLAGS) $(INC) -o crc crc.c
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$(CMD) crc_tb.py
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scrambler_tb:
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$(CC) $(CFLAGS) $(INC) -o scrambler scrambler.c
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scrambler_tb: scrambler
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$(CMD) scrambler_tb.py
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cont_tb:
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@ -26,7 +25,7 @@ link_tb:
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command_tb:
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$(CMD) command_tb.py
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bist_tb:
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bist_tb: scrambler
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$(CMD) bist_tb.py
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striping_tb:
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@ -35,5 +34,8 @@ striping_tb:
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mirroring_tb:
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$(CMD) mirroring_tb.py
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scrambler: scrambler.c
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$(CC) $(CFLAGS) $(INC) -o $@ $<
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clean:
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rm crc scrambler *.vcd
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rm -f crc scrambler *.vcd
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Reference in New Issue