liteusb: make oe_n optional on ft2232h phy
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ed5746a1fe
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@ -3,7 +3,7 @@ from migen.flow.actor import *
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from migen.actorlib.fifo import AsyncFIFO
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from migen.actorlib.fifo import AsyncFIFO
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from migen.fhdl.specials import *
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from migen.fhdl.specials import *
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from liteusb.ftdi.std import *
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from misoclib.com.liteusb.common import *
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class FtdiPHY(Module):
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class FtdiPHY(Module):
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def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16):
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def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16):
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@ -100,7 +100,12 @@ class FtdiPHY(Module):
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data_r = Signal(dw)
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data_r = Signal(dw)
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data_oe = Signal()
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data_oe = Signal()
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pads.oe_n.reset = 1
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if hasattr(pads, "oe_n"):
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pads_oe_n = pads.oe_n
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else:
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pads_oe_n = Signal()
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pads_oe_n.reset = 1
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pads.rd_n.reset = 1
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pads.rd_n.reset = 1
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pads.wr_n.reset = 1
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pads.wr_n.reset = 1
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@ -108,14 +113,14 @@ class FtdiPHY(Module):
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If(fsm.ongoing("READ"),
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If(fsm.ongoing("READ"),
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data_oe.eq(0),
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data_oe.eq(0),
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pads.oe_n.eq(0),
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pads_oe_n.eq(0),
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pads.rd_n.eq(~wants_read),
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pads.rd_n.eq(~wants_read),
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pads.wr_n.eq(1)
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pads.wr_n.eq(1)
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).Elif(fsm.ongoing("WRITE"),
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).Elif(fsm.ongoing("WRITE"),
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data_oe.eq(1),
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data_oe.eq(1),
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pads.oe_n.eq(1),
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pads_oe_n.eq(1),
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pads.rd_n.eq(1),
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pads.rd_n.eq(1),
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pads.wr_n.eq(~wants_write),
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pads.wr_n.eq(~wants_write),
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@ -124,7 +129,7 @@ class FtdiPHY(Module):
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).Else(
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).Else(
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data_oe.eq(1),
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data_oe.eq(1),
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pads.oe_n.eq(~fsm.ongoing("WTR")),
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pads_oe_n.eq(~fsm.ongoing("WTR")),
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pads.rd_n.eq(1),
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pads.rd_n.eq(1),
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pads.wr_n.eq(1)
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pads.wr_n.eq(1)
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),
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),
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