liteusb: fix imports

misoclib/com/liteusb/core/__init__.py

@@ -1,4 +1,4 @@
-from liteusb.ftdi.uart import FtdiUART
-from liteusb.ftdi.dma import FtdiDMA
-from liteusb.ftdi.com import FtdiCom
-from liteusb.ftdi.crc import FtdiCRC32
+from misoclib.com.liteusb.frontend.uart import FtdiUART
+from misoclib.com.liteusb.frontend.dma import FtdiDMA
+from misoclib.com.liteusb.core.com import FtdiCom
+from misoclib.com.liteusb.core.crc import FtdiCRC32

misoclib/com/liteusb/core/com.py

@@ -1,11 +1,11 @@
 from migen.fhdl.std import *
 from migen.flow.actor import *
 
-from liteusb.ftdi.std import *
-from liteusb.ftdi.crossbar import FtdiCrossbar
-from liteusb.ftdi.packetizer import FtdiPacketizer
-from liteusb.ftdi.depacketizer import FtdiDepacketizer
-from liteusb.ftdi.phy import FtdiPHY
+from misoclib.com.liteusb.common import *
+from misoclib.com.liteusb.frontend.crossbar import FtdiCrossbar
+from misoclib.com.liteusb.core.packetizer import FtdiPacketizer
+from misoclib.com.liteusb.core.depacketizer import FtdiDepacketizer
+from misoclib.com.liteusb.phy.ft2232h import FtdiPHY
 
 class FtdiCom(Module):
 	def __init__(self, pads, *ports):

misoclib/com/liteusb/core/crc.py

@@ -1,4 +1,3 @@
-
 from collections import OrderedDict
 from migen.fhdl.std import *
 from migen.genlib.fsm import FSM, NextState
@@ -7,7 +6,7 @@ from migen.genlib.misc import chooser, optree
 from migen.flow.actor import Sink, Source
 from migen.actorlib.fifo import SyncFIFO
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class CRCEngine(Module):
 	"""Cyclic Redundancy Check Engine

misoclib/com/liteusb/core/depacketizer.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.actorlib.structuring import *
 from migen.genlib.fsm import FSM, NextState
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiDepacketizer(Module):
 	def __init__(self, timeout=10):

misoclib/com/liteusb/core/packetizer.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.actorlib.structuring import *
 from migen.genlib.fsm import FSM, NextState
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiPacketizer(Module):
 	def __init__(self):

misoclib/com/liteusb/frontend/crossbar.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.roundrobin import *
 from migen.genlib.record import Record
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiCrossbar(Module):
 	def __init__(self, masters, slave=None):

misoclib/com/liteusb/frontend/dma.py

@@ -8,7 +8,7 @@ from migen.genlib.record import Record
 
 from misoclib.mem.sdram.frontend import dma_lasmi
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiDMAWriter(Module, AutoCSR):
 	def __init__(self, lasmim):

misoclib/com/liteusb/frontend/uart.py

@@ -3,7 +3,7 @@ from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.genlib.fifo import SyncFIFOBuffered
 
-from liteusb.ftdi.std import *
+from misoclib.com.liteusb.common import *
 
 class FtdiUART(Module, AutoCSR):
 	def __init__(self, tag, fifo_depth=64):