Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/add_spi_flash: Reduce default_divisor.

This commit is contained in:
Florent Kermarrec 2021-07-30 12:32:57 +02:00
parent 6100620634
commit c80d5723c9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/integration/soc.py
View File

@ -1497,7 +1497,7 @@ class LiteXSoC(SoC):
self.check_if_exists(name + "_phy")
self.check_if_exists(name + "_mmap")
spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=max(int(self.sys_clk_freq/clk_freq), 2))
spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=int(self.sys_clk_freq/clk_freq))
spiflash_core = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs)
setattr(self.submodules, name + "_phy", spiflash_phy)
setattr(self.submodules, name + "_core", spiflash_core)