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soc/cores/hyperbus: Expose burst_timer to ease debug.

This commit is contained in:
Florent Kermarrec 2023-01-10 11:09:45 +01:00
parent 1f2a44516e
commit c834387965
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/hyperbus.py
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@ -65,7 +65,7 @@ class HyperRAM(Module):
# Burst Timer ------------------------------------------------------------------------------ # Burst Timer ------------------------------------------------------------------------------
sys_clk_freq = 10e6 if sys_clk_freq is None else sys_clk_freq sys_clk_freq = 10e6 if sys_clk_freq is None else sys_clk_freq
burst_timer = WaitTimer(int(sys_clk_freq*self.tCSM)) burst_timer = WaitTimer(int(sys_clk_freq*self.tCSM))
self.submodules += burst_timer self.submodules.burst_timer = burst_timer
# Clock Generation (sys_clk/4) ------------------------------------------------------------- # Clock Generation (sys_clk/4) -------------------------------------------------------------
self.sync += clk_phase.eq(clk_phase + 1) self.sync += clk_phase.eq(clk_phase + 1)