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Merge pull request #1632 from jorislee/master

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soc/cores/cpu/vexriscv_smp/core.py: fix variants for external incoming values and remove default timer0 and uart in standard mode.
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enjoy-digital 2023-03-06 09:03:55 +01:00 committed by GitHub
commit c8dcc39957
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1 changed files with 9 additions and 8 deletions
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litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -275,7 +275,7 @@ class VexRiscvSMP(CPU):
def __init__(self, platform, variant):
self.platform = platform
self.variant = "linux"
self.variant = variant
self.human_name = self.human_name + "-" + self.variant.upper()
self.reset = Signal()
self.jtag_clk = Signal()
@ -388,15 +388,16 @@ class VexRiscvSMP(CPU):
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
def add_soc_components(self, soc):
# Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)
if self.variant == "linux":
# Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)
soc.irq.add("uart", n=0)
soc.irq.add("timer0", n=1)
soc.irq.add("uart", n=0)
soc.irq.add("timer0", n=1)
# Add OpenSBI region.
soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
# Add OpenSBI region.
soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
# Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)