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integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt").

This commit is contained in:
Florent Kermarrec 2020-11-30 10:17:03 +01:00
parent 146068b048
commit c8fcaaea2d
2 changed files with 5 additions and 5 deletions
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6
litex/soc/integration/soc.py
View File

@ -905,7 +905,7 @@ class SoC(Module):
self.check_if_exists(name) self.check_if_exists(name)
setattr(self.submodules, name, Timer()) setattr(self.submodules, name, Timer())
self.csr.add(name, use_loc_if_exists=True) self.csr.add(name, use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"): if self.irq.enabled:
self.irq.add(name, use_loc_if_exists=True) self.irq.add(name, use_loc_if_exists=True)
# SoC finalization ----------------------------------------------------------------------------- # SoC finalization -----------------------------------------------------------------------------
@ -1141,7 +1141,7 @@ class LiteXSoC(SoC):
self.csr.add("uart_phy", use_loc_if_exists=True) self.csr.add("uart_phy", use_loc_if_exists=True)
self.csr.add("uart", use_loc_if_exists=True) self.csr.add("uart", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"): if self.irq.enabled:
self.irq.add("uart", use_loc_if_exists=True) self.irq.add("uart", use_loc_if_exists=True)
else: else:
self.add_constant("UART_POLLING") self.add_constant("UART_POLLING")
@ -1333,7 +1333,7 @@ class LiteXSoC(SoC):
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False) ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False)
self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
self.csr.add(name, use_loc_if_exists=True) self.csr.add(name, use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"): if self.irq.enabled:
self.irq.add(name, use_loc_if_exists=True) self.irq.add(name, use_loc_if_exists=True)
# Timing constraints # Timing constraints
if hasattr(phy, "crg"): if hasattr(phy, "crg"):

4
litex/tools/litex_sim.py
View File

@ -236,7 +236,7 @@ class SimSoC(SoCCore):
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac") self.add_csr("ethmac")
if hasattr(self.cpu, "interrupt"): if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True) self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet # HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8)
@ -262,7 +262,7 @@ class SimSoC(SoCCore):
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac") self.add_csr("ethmac")
if hasattr(self.cpu, "interrupt"): if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True) self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------