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fhdl/module: support clock domain remapping of submodules
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a94bf3b2c5
commit
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1 changed files with 15 additions and 3 deletions
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@ -67,11 +67,11 @@ class _ModuleSpecials(_ModuleProxy, _ModuleForwardAttr):
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class _ModuleSubmodules(_ModuleProxy):
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def __setattr__(self, name, value):
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self._fm._submodules += [(name, e) for e in _flat_list(value)]
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self._fm._submodules += [(name, e, dict()) for e in _flat_list(value)]
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setattr(self._fm, name, value)
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def __iadd__(self, other):
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self._fm._submodules += [(None, e) for e in _flat_list(other)]
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self._fm._submodules += [(None, e, dict()) for e in _flat_list(other)]
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return self
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class _ModuleClockDomains(_ModuleProxy, _ModuleForwardAttr):
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@ -130,8 +130,20 @@ class Module:
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else:
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object.__setattr__(self, name, value)
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def add_submodule(self, submodule, cd_remapping=dict(), name=None):
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if isinstance(cd_remapping, str):
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cd_remapping = {"sys": cd_remapping}
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if name is not None:
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setattr(self, name, submodule)
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self._submodules.append((name, submodule, cd_remapping))
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def _collect_submodules(self):
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r = [(name, submodule.get_fragment()) for name, submodule in self._submodules]
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r = []
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for name, submodule, cd_remapping in self._submodules:
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f = submodule.get_fragment()
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for old, new in cd_remapping.items():
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rename_clock_domain(f, old, new)
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r.append((name, f))
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self._submodules = []
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return r
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