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bios/sdram: use burstdet detection for ECP5DDRPHY init

This commit is contained in:
Florent Kermarrec 2019-03-05 12:26:10 +01:00
parent 2ebfab5e1f
commit ca63db4040
1 changed files with 24 additions and 2 deletions
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26
litex/soc/software/bios/sdram.c
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@ -210,13 +210,14 @@ void sdrwr(char *startaddr)
#if defined (USDDRPHY) #if defined (USDDRPHY)
#define ERR_DDRPHY_DELAY 512 #define ERR_DDRPHY_DELAY 512
#define ERR_DDRPHY_BITSLIP DFII_NPHASES*2
#elif defined (ECP5DDRPHY) #elif defined (ECP5DDRPHY)
#define ERR_DDRPHY_DELAY 8 #define ERR_DDRPHY_DELAY 8
#define ERR_DDRPHY_BITSLIP 1
#else #else
#define ERR_DDRPHY_DELAY 32 #define ERR_DDRPHY_DELAY 32
#endif
#define ERR_DDRPHY_BITSLIP DFII_NPHASES*2 #define ERR_DDRPHY_BITSLIP DFII_NPHASES*2
#endif
#define NBMODULES DFII_PIX_DATA_SIZE*DFII_NPHASES/8 #define NBMODULES DFII_PIX_DATA_SIZE*DFII_NPHASES/8
@ -461,6 +462,9 @@ static int read_level_scan(int module, int bitslip)
int show = 1; int show = 1;
#ifdef USDDRPHY #ifdef USDDRPHY
show = (j%16 == 0); show = (j%16 == 0);
#endif
#ifdef ECP5DDRPHY
ddrphy_burstdet_clr_write(1);
#endif #endif
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15); cdelay(15);
@ -471,6 +475,10 @@ static int read_level_scan(int module, int bitslip)
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1]) if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1])
working = 0; working = 0;
} }
#ifdef ECP5DDRPHY
if (((ddrphy_burstdet_seen_read() >> module) & 0x1) != 1)
working = 0;
#endif
if (show) if (show)
printf("%d", working); printf("%d", working);
score += working; score += working;
@ -526,6 +534,9 @@ static void read_level(int module)
delay = 0; delay = 0;
read_delay_rst(module); read_delay_rst(module);
while(1) { while(1) {
#ifdef ECP5DDRPHY
ddrphy_burstdet_clr_write(1);
#endif
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15); cdelay(15);
working = 1; working = 1;
@ -535,6 +546,10 @@ static void read_level(int module)
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1]) if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1])
working = 0; working = 0;
} }
#ifdef ECP5DDRPHY
if (((ddrphy_burstdet_seen_read() >> module) & 0x1) != 1)
working = 0;
#endif
if(working) if(working)
break; break;
delay++; delay++;
@ -557,6 +572,9 @@ static void read_level(int module)
/* Find largest working delay */ /* Find largest working delay */
while(1) { while(1) {
#ifdef ECP5DDRPHY
ddrphy_burstdet_clr_write(1);
#endif
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15); cdelay(15);
working = 1; working = 1;
@ -566,6 +584,10 @@ static void read_level(int module)
if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1]) if(MMPTR(sdram_dfii_pix_rddata_addr[p]+4*(2*NBMODULES-module-1)) != prs[DFII_PIX_DATA_SIZE*p+2*NBMODULES-module-1])
working = 0; working = 0;
} }
#ifdef ECP5DDRPHY
if (((ddrphy_burstdet_seen_read() >> module) & 0x1) != 1)
working = 0;
#endif
if(!working) if(!working)
break; break;
delay++; delay++;