boards/targets: add default rom/ram configuration for arty

2015-12-01 10:20:16 +01:00 · 2015-12-01 10:20:16 +01:00 · ca6b9aa6e3
parent e5d35ccb6d
commit ca6b9aa6e3
1 changed files with 5 additions and 1 deletions
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@ -72,7 +72,11 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
    def __init__(self, **kwargs):
        platform = arty.Platform()
-        SoCCore.__init__(self, platform, clk_freq=100*1000000, **kwargs)
+        SoCCore.__init__(self, platform, clk_freq=100*1000000,
+                         integrated_rom_size=0x8000,
+                         integrated_sram_size=0x8000,
+                         integrated_main_ram_size=0x10000,
+                         **kwargs)

        self.submodules.crg = _CRG(platform)