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boards/targets: add default rom/ram configuration for arty

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This commit is contained in:
Florent Kermarrec 2015-12-01 10:20:16 +01:00
parent e5d35ccb6d
commit ca6b9aa6e3
1 changed files with 5 additions and 1 deletions
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6
litex/boards/targets/arty.py
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@ -72,7 +72,11 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, **kwargs):
platform = arty.Platform()
SoCCore.__init__(self, platform, clk_freq=100*1000000, **kwargs)
SoCCore.__init__(self, platform, clk_freq=100*1000000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
integrated_main_ram_size=0x10000,
**kwargs)
self.submodules.crg = _CRG(platform)