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fhdl: support forwarding of bidirectional signals from instance ports

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This commit is contained in:
Sebastien Bourdeauducq 2012-02-16 18:34:32 +01:00
parent c08687b9c6
commit ca7056b07f
4 changed files with 16 additions and 11 deletions
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7
examples/lm32_inst.py
View file

@ -32,10 +32,9 @@ class LM32:
("D_ACK_I", BV(1)), ("D_ACK_I", BV(1)),
("D_ERR_I", BV(1)), ("D_ERR_I", BV(1)),
("D_RTY_I", BV(1))], ("D_RTY_I", BV(1))],
[], clkport="clk_i",
"clk_i", rstport="rst_i",
"rst_i", name="lm32")
"lm32")
def get_fragment(self): def get_fragment(self):
return Fragment(instances=[self.inst]) return Fragment(instances=[self.inst])

3
migen/fhdl/structure.py
View file

@ -209,7 +209,7 @@ class Case:
# #
class Instance: class Instance:
def __init__(self, of, outs=[], ins=[], parameters=[], clkport="", rstport="", name=""): def __init__(self, of, outs=[], ins=[], inouts=[], parameters=[], clkport="", rstport="", name=""):
self.of = of self.of = of
if name: if name:
self.name_override = name self.name_override = name
@ -224,6 +224,7 @@ class Instance:
raise TypeError raise TypeError
self.outs = dict(map(process_io, outs)) self.outs = dict(map(process_io, outs))
self.ins = dict(map(process_io, ins)) self.ins = dict(map(process_io, ins))
self.inouts = dict(map(process_io, inouts))
self.parameters = parameters self.parameters = parameters
self.clkport = clkport self.clkport = clkport
self.rstport = rstport self.rstport = rstport

6
migen/fhdl/tools.py
View file

@ -73,9 +73,9 @@ def group_by_targets(sl):
groups.append((targets, [statement])) groups.append((targets, [statement]))
return groups return groups
def list_inst_ios(i, ins, outs): def list_inst_ios(i, ins, outs, inouts):
if isinstance(i, Fragment): if isinstance(i, Fragment):
return list_inst_ios(i.instances, ins, outs) return list_inst_ios(i.instances, ins, outs, inouts)
else: else:
l = [] l = []
for x in i: for x in i:
@ -83,6 +83,8 @@ def list_inst_ios(i, ins, outs):
l += x.ins.values() l += x.ins.values()
if outs: if outs:
l += x.outs.values() l += x.outs.values()
if inouts:
l += x.inouts.values()
return set(l) return set(l)
def list_mem_ios(m, ins, outs): def list_mem_ios(m, ins, outs):

11
migen/fhdl/verilog.py
View file

@ -103,8 +103,9 @@ def _list_comb_wires(f):
return r return r
def _printheader(f, ios, name, ns): def _printheader(f, ios, name, ns):
sigs = list_signals(f) | list_inst_ios(f, True, True) | list_mem_ios(f, True, True) sigs = list_signals(f) | list_inst_ios(f, True, True, True) | list_mem_ios(f, True, True)
inst_mem_outs = list_inst_ios(f, False, True) | list_mem_ios(f, False, True) inst_mem_outs = list_inst_ios(f, False, True, False) | list_mem_ios(f, False, True)
inouts = list_inst_ios(f, False, False, True)
targets = list_targets(f) | inst_mem_outs targets = list_targets(f) | inst_mem_outs
wires = _list_comb_wires(f) | inst_mem_outs wires = _list_comb_wires(f) | inst_mem_outs
r = "module " + name + "(\n" r = "module " + name + "(\n"
@ -113,7 +114,9 @@ def _printheader(f, ios, name, ns):
if not firstp: if not firstp:
r += ",\n" r += ",\n"
firstp = False firstp = False
if sig in targets: if sig in inouts:
r += "\tinout " + _printsig(ns, sig)
elif sig in targets:
if sig in wires: if sig in wires:
r += "\toutput " + _printsig(ns, sig) r += "\toutput " + _printsig(ns, sig)
else: else:
@ -230,7 +233,7 @@ def convert(f, ios=set(), name="top",
ios |= f.pads ios |= f.pads
ns = build_namespace(list_signals(f) \ ns = build_namespace(list_signals(f) \
| list_inst_ios(f, True, True) \ | list_inst_ios(f, True, True, True) \
| list_mem_ios(f, True, True) \ | list_mem_ios(f, True, True) \
| ios) | ios)