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dvisampler/chansync: fix FIFO width

This commit is contained in:
Sebastien Bourdeauducq 2013-05-05 12:58:24 +02:00
parent ad01dc8a74
commit cb008a061c
1 changed files with 2 additions and 2 deletions
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4
milkymist/dvisampler/chansync.py
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@ -2,7 +2,7 @@ from migen.fhdl.structure import *
from migen.fhdl.module import Module from migen.fhdl.module import Module
from migen.genlib.cdc import MultiReg from migen.genlib.cdc import MultiReg
from migen.genlib.fifo import SyncFIFO from migen.genlib.fifo import SyncFIFO
from migen.genlib.record import Record from migen.genlib.record import Record, layout_len
from migen.genlib.misc import optree from migen.genlib.misc import optree
from migen.bank.description import * from migen.bank.description import *
@ -27,7 +27,7 @@ class ChanSync(Module, AutoCSR):
### ###
fifo = SyncFIFO(10, depth) fifo = SyncFIFO(layout_len(channel_layout), depth)
self.add_submodule(fifo, "pix") self.add_submodule(fifo, "pix")
self.comb += [ self.comb += [
fifo.we.eq(self.valid_i), fifo.we.eq(self.valid_i),