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integration/soc: add ethphy CSR in target.

This commit is contained in:
Florent Kermarrec 2020-03-02 08:42:59 +01:00
parent f27225c2de
commit cb0371b330
2 changed files with 1 additions and 2 deletions
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1
litex/boards/targets/nexys4ddr.py
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@ -80,6 +80,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.ethphy = LiteEthPHYRMII( self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth")) pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy) self.add_ethernet(phy=self.ethphy)
def add_sdcard(self): def add_sdcard(self):

2
litex/soc/integration/soc.py
View File

@ -1014,8 +1014,6 @@ class LiteXSoC(SoC):
def add_ethernet(self, phy): def add_ethernet(self, phy):
# Imports # Imports
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
# PHY
self.add_csr("ethphy")
# MAC # MAC
self.submodules.ethmac = LiteEthMAC( self.submodules.ethmac = LiteEthMAC(
phy = phy, phy = phy,