integration/soc: add ethphy CSR in target.

litex/boards/targets/nexys4ddr.py

@@ -80,6 +80,7 @@ class BaseSoC(SoCSDRAM):
             self.submodules.ethphy = LiteEthPHYRMII(
                 clock_pads = self.platform.request("eth_clocks"),
                 pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
     def add_sdcard(self):

litex/soc/integration/soc.py

@@ -1014,8 +1014,6 @@ class LiteXSoC(SoC):
     def add_ethernet(self, phy):
         # Imports
         from liteeth.mac import LiteEthMAC
-        # PHY
-        self.add_csr("ethphy")
         # MAC
         self.submodules.ethmac = LiteEthMAC(
             phy        = phy,