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cores/clock/xilinx: Cosmetic cleanup on Instances.

This commit is contained in:
Florent Kermarrec 2021-05-19 22:20:04 +02:00
parent 12b27f961c
commit cbb75b852e
4 changed files with 77 additions and 32 deletions
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7
litex/soc/cores/clock/xilinx_s6.py
View File

@ -32,9 +32,14 @@ class S6PLL(XilinxClocking):
config = self.compute_config()
pll_fb = Signal()
self.params.update(
# Global.
p_SIM_DEVICE = "SPARTAN6",
p_BANDWIDTH = "OPTIMIZED",
p_COMPENSATION = "INTERNAL",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO.
p_REF_JITTER = .01, p_CLK_FEEDBACK="CLKFBOUT",
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKIN2_PERIOD = 0.,
@ -42,11 +47,9 @@ class S6PLL(XilinxClocking):
p_CLKFBOUT_PHASE = 0.,
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKINSEL = 1,
i_RST = self.reset,
i_CLKIN1 = self.clkin,
i_CLKFBIN = pll_fb,
o_CLKFBOUT = pll_fb,
o_LOCKED = self.locked,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]

34
litex/soc/cores/clock/xilinx_s7.py
View File

@ -31,12 +31,19 @@ class S7PLL(XilinxClocking):
config = self.compute_config()
pll_fb = Signal()
self.params.update(
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
# Global.
p_STARTUP_WAIT = "FALSE",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# VCO.
p_REF_JITTER1 = 0.01,
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKFBOUT_MULT = config["clkfbout_mult"],
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKIN1 = self.clkin,
i_CLKFBIN = pll_fb,
o_CLKFBOUT = pll_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
@ -71,12 +78,19 @@ class S7MMCM(XilinxClocking):
config = self.compute_config()
mmcm_fb = Signal()
self.params.update(
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
# Global.
p_BANDWIDTH = "OPTIMIZED",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
# VCO.
p_REF_JITTER1 = 0.01,
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F = config["clkfbout_mult"],
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKIN1 = self.clkin,
i_CLKFBIN = mmcm_fb,
o_CLKFBOUT = mmcm_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
if n == 0:

34
litex/soc/cores/clock/xilinx_us.py
View File

@ -36,12 +36,19 @@ class USPLL(XilinxClocking):
config = self.compute_config()
pll_fb = Signal()
self.params.update(
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
# Global.
p_STARTUP_WAIT = "FALSE",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# VCO.
p_REF_JITTER1 = 0.01,
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKFBOUT_MULT = config["clkfbout_mult"],
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKIN1 = self.clkin,
i_CLKFBIN = pll_fb,
o_CLKFBOUT = pll_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
@ -74,12 +81,19 @@ class USMMCM(XilinxClocking):
config = self.compute_config()
mmcm_fb = Signal()
self.params.update(
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
# Global.
p_BANDWIDTH = "OPTIMIZED",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
# VCO.
p_REF_JITTER1 = 0.01,
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F = config["clkfbout_mult"],
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKIN1 = self.clkin,
i_CLKFBIN = mmcm_fb,
o_CLKFBOUT = mmcm_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
if n == 0:

34
litex/soc/cores/clock/xilinx_usp.py
View File

@ -36,12 +36,19 @@ class USPPLL(XilinxClocking):
config = self.compute_config()
pll_fb = Signal()
self.params.update(
p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
# Global.
p_STARTUP_WAIT = "FALSE",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# VCO.
p_REF_JITTER1 = 0.01,
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKFBOUT_MULT = config["clkfbout_mult"],
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKIN1 = self.clkin,
i_CLKFBIN = pll_fb,
o_CLKFBOUT = pll_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
@ -74,12 +81,19 @@ class USPMMCM(XilinxClocking):
config = self.compute_config()
mmcm_fb = Signal()
self.params.update(
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
# Global.
p_BANDWIDTH = "OPTIMIZED",
i_RST = self.reset,
o_LOCKED = self.locked,
# VCO
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
# VCO.
p_REF_JITTER1 = 0.01,
p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
p_CLKFBOUT_MULT_F = config["clkfbout_mult"],
p_DIVCLK_DIVIDE = config["divclk_divide"],
i_CLKIN1 = self.clkin,
i_CLKFBIN = mmcm_fb,
o_CLKFBOUT = mmcm_fb,
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
if n == 0: