soc_core: use add_rom

2020-02-10 17:43:29 +01:00 · 2020-02-10 17:43:29 +01:00 · cbcd953dd7
parent 487ac3da9a
commit cbcd953dd7
1 changed files with 1 additions and 2 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -147,8 +147,7 @@ class SoCCore(LiteXSoC):

        # Add integrated ROM
        if integrated_rom_size:
-            self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
-            self.register_rom(self.rom.bus, integrated_rom_size)
+            self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init)

        # Add integrated SRAM
        if integrated_sram_size: