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soc_core: use add_rom

This commit is contained in:
Florent Kermarrec 2020-02-10 17:43:29 +01:00
parent 487ac3da9a
commit cbcd953dd7
1 changed files with 1 additions and 2 deletions
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3
litex/soc/integration/soc_core.py
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@ -147,8 +147,7 @@ class SoCCore(LiteXSoC):
# Add integrated ROM # Add integrated ROM
if integrated_rom_size: if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM # Add integrated SRAM
if integrated_sram_size: if integrated_sram_size: