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soc/integration: Improve error handling for framebuffer without sdram

This commit is contained in:
David A Roberts 2024-04-04 17:43:27 +10:00
parent e9f6fef3d4
commit ccbfce920a
1 changed files with 9 additions and 2 deletions
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11
litex/soc/integration/soc.py
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@ -2367,10 +2367,14 @@ class LiteXSoC(SoC):
size = 0x800000 size = 0x800000
# If the intended region isn't contained in the main_ram region, adjust it to fit. # If the intended region isn't contained in the main_ram region, adjust it to fit.
main_ram_region = self.bus.regions.get("main_ram", None) main_ram_region = self.bus.regions.get("main_ram", None)
if main_ram_region is not None and not ( if main_ram_region is None:
self.logger.error("Video framebuffer requires SDRAM")
raise SoCError()
contained_in_main_ram = (
main_ram_region.origin < base main_ram_region.origin < base
and base + size < main_ram_region.origin + main_ram_region.size and base + size < main_ram_region.origin + main_ram_region.size
): )
if not contained_in_main_ram:
size = min(size, main_ram_region.size // 2) size = min(size, main_ram_region.size // 2)
base = main_ram_region.origin + main_ram_region.size - size base = main_ram_region.origin + main_ram_region.size - size
self.bus.add_region(name, SoCRegion( self.bus.add_region(name, SoCRegion(
@ -2381,6 +2385,9 @@ class LiteXSoC(SoC):
base = self.bus.regions[name].origin base = self.bus.regions[name].origin
hres = int(timings.split("@")[0].split("x")[0]) hres = int(timings.split("@")[0].split("x")[0])
vres = int(timings.split("@")[0].split("x")[1]) vres = int(timings.split("@")[0].split("x")[1])
if not hasattr(self, "sdram"):
self.logger.error("Video framebuffer requires SDRAM")
raise SoCError()
vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(), vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(),
hres = hres, hres = hres,
vres = vres, vres = vres,