litex/gen/verilog: use format_constant
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@ -29,6 +29,7 @@ from migen.fhdl.specials import Instance, Memory
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from litex.gen import LiteXContext
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from litex.gen import LiteXContext
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from litex.gen.fhdl.namer import build_signal_namespace
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from litex.gen.fhdl.namer import build_signal_namespace
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from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer
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from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer
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from litex.gen.format import format_constant
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from litex.build.tools import get_litex_git_revision
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from litex.build.tools import get_litex_git_revision
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@ -165,10 +166,10 @@ _ieee_1800_2017_verilog_reserved_keywords = {
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# Print Constant -----------------------------------------------------------------------------------
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# Print Constant -----------------------------------------------------------------------------------
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def _generate_constant(node):
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def _generate_constant(node):
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return "{sign}{bits}'d{value}".format(
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return "{sign}{bits}'{value}".format(
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sign = "" if node.value >= 0 else "-",
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sign = "" if node.value >= 0 else "-",
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bits = str(node.nbits),
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bits = str(node.nbits),
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value = abs(node.value),
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value = format_constant(abs(node.value), verilog=True),
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), node.signed
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), node.signed
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# Print Signal -------------------------------------------------------------------------------------
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# Print Signal -------------------------------------------------------------------------------------
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