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build/efinix/ifacewriter: Titanium PLL's feedback clock

This commit is contained in:
Gwenhael Goavec-Merou 2023-12-19 21:25:59 +01:00
parent 048c42820c
commit cd503bc9af
1 changed files with 9 additions and 3 deletions
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12
litex/build/efinix/ifacewriter.py
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@ -281,7 +281,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
if block["version"] == "V3":
cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \
.format(name, block["resource"], block["input_clock_pad"], block["clock_no"])
cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name)
else:
cmd += 'design.set_property("{}","EXT_CLK","EXT_CLK{}","PLL")\n'.format(name, block["clock_no"])
@ -329,7 +328,14 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
else:
cmd += 'design.set_property("{}","CLKOUT{}_PHASE_SETTING","{}","PLL")\n'.format(name, i, clock[2] // 45)
if block["feedback"] == -1:
# Titanium has always a feedback (local: CLK0, CORE: any output)
if block["version"] == "V3":
feedback_clk = block["feedback"]
cmd += 'design.set_property("{}", "FEEDBACK_MODE", "{}", "PLL")\n'.format(name, "LOCAL" if feedback_clk < 1 else "CORE")
cmd += 'design.set_property("{}", "FEEDBACK_CLK", "CLK{}", "PLL")\n'.format(name, 0 if feedback_clk < 1 else feedback_clk)
# auto_calc_pll_clock is always working with Titanium and only working when feedback is unused for Trion
if block["feedback"] == -1 or block["version"] == "V3":
cmd += "target_freq = {\n"
for i, clock in enumerate(block["clk_out"]):
cmd += ' "CLKOUT{}_FREQ": "{}",\n'.format(i, clock[1] / 1e6)
@ -358,7 +364,7 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
cmd += 'print("#### {} ####")\n'.format(name)
cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name)
cmd += 'pprint.pprint(clksrc_info)\n'
cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE"]\n'
cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE", "FEEDBACK_MODE", "FEEDBACK_CLK"]\n'
for i, clock in enumerate(block["clk_out"]):
cmd += 'clock_source_prop += ["CLKOUT{}_FREQ", "CLKOUT{}_PHASE", "CLKOUT{}_EN"]\n'.format(i, i, i)
cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)