cpu/lm32: add missing buses

2019-10-12 19:20:50 +02:00 · 2019-10-12 19:20:50 +02:00 · cd8213b988
parent 5a0358754d
commit cd8213b988
1 changed files with 1 additions and 0 deletions
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@ -40,6 +40,7 @@ class LM32(CPU):
        self.ibus      = i = wishbone.Interface()
        self.dbus      = d = wishbone.Interface()
        self.interrupt = Signal(32)
+        self.buses     = [i, d]

        # # #