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s6ddrphy: fix read latency

This commit is contained in:
Sebastien Bourdeauducq 2013-06-11 16:02:34 +02:00
parent 4d0c80ca1a
commit ce2f08844a
2 changed files with 2 additions and 2 deletions
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2
top.py
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@ -44,7 +44,7 @@ sdram_timing = lasmicon.TimingSettings(
tRFC=ns(70), tRFC=ns(70),
CL=3, CL=3,
read_latency=4, read_latency=5,
write_latency=0, write_latency=0,
read_time=32, read_time=32,

2
verilog/s6ddrphy/s6ddrphy.v
View File

@ -7,7 +7,7 @@
* *
* Assert dfi_rddata_en in the same cycle as the read * Assert dfi_rddata_en in the same cycle as the read
* command. The data will come back on dfi_rddata * command. The data will come back on dfi_rddata
* 4 cycles later, along with the assertion of * 5 cycles later, along with the assertion of
* dfi_rddata_valid. * dfi_rddata_valid.
* *
* This PHY only supports CAS Latency 3. * This PHY only supports CAS Latency 3.