soc/cores/uart: add FT245 FIFO mode support (sync & async)
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@ -13,6 +13,7 @@ from litex.soc.interconnect.csr_eventmanager import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
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# RS232 PHY ----------------------------------------------------------------------------------------
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class RS232PHYInterface:
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def __init__(self):
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@ -157,6 +158,7 @@ class RS232PHYModel(Module):
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pads.sink_ready.eq(self.source.ready)
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]
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# UART ---------------------------------------------------------------------------------------------
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def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
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if sink_cd != source_cd:
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@ -165,6 +167,18 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
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else:
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return stream.SyncFIFO([("data", 8)], depth, buffered=True)
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def UARTPHY(pads, clk_freq, baudrate):
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# FT245 async FIFO mode (baudrate ignored)
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if hasattr(pads, "rd_n") and hasattr(pads, "wr_n"):
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from litex.soc.cores.usb_fifo import FT245PHYAsynchronous
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return FT245PHYAsynchronous(pads, clk_freq)
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# FT245 sync FIFO mode (baudrate ignored)
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if hasattr(pads, "rd_n") and hasattr(pads, "wr_n") and hasattr(pads, "oe_n"):
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from litex.soc.cores.usb_fifo import FT245PHYSynchronous
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return FT245PHYSynchronous(pads, clk_freq)
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# RS232
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else:
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return RS232PHY(pads, clk_freq, baudrate)
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class UART(Module, AutoCSR):
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def __init__(self, phy,
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@ -315,7 +315,7 @@ class SoCCore(Module):
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if uart_stub:
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self.submodules.uart = uart.UARTStub()
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else:
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self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
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self.add_csr("uart_phy", allow_user_defined=True)
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self.add_csr("uart", allow_user_defined=True)
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