cpu/VexRiscv_SMP add --wishbone-force-32b option
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@ -260,7 +260,7 @@ class VexRiscvSMP(CPU):
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gen_args.append(f"--aes-instruction={VexRiscvSMP.aes_instruction}")
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gen_args.append(f"--out-of-order-decoder={VexRiscvSMP.out_of_order_decoder}")
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gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
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gen_args.append(f"--wishbone-force-32b={VexRiscvSMP.wishbone_force_32b}")
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if(VexRiscvSMP.wishbone_force_32b): gen_args.append(f"--wishbone-force-32b={VexRiscvSMP.wishbone_force_32b}")
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gen_args.append(f"--fpu={VexRiscvSMP.with_fpu}")
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gen_args.append(f"--cpu-per-fpu={VexRiscvSMP.cpu_per_fpu}")
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gen_args.append(f"--rvc={VexRiscvSMP.with_rvc}")
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