fix soc/integration/soc_core.py

2015-11-14 02:44:12 +01:00 · 2015-11-14 02:44:12 +01:00 · cf4c7da2e7
parent 032f5a9620
commit cf4c7da2e7
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -197,7 +197,7 @@ class SoCCore(Module):
        # Interrupts
        for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
            if hasattr(self, k):
-                self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
+                self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)

    def build(self, *args, **kwargs):
        self.platform.build(self, *args, **kwargs)