pytholite: support signed registers

migen/pytholite/compiler.py

@@ -96,12 +96,12 @@ class _Compiler:
 		if callee == transel.Register:
 			if len(value.args) != 1:
 				raise TypeError("Register() takes exactly 1 argument")
-			nbits = ast.literal_eval(value.args[0])
+			bits_sign = ast.literal_eval(value.args[0])
 			if isinstance(node.targets[0], ast.Name):
 				targetname = node.targets[0].id
 			else:
 				targetname = "unk"
-			reg = ImplRegister(targetname, nbits)
+			reg = ImplRegister(targetname, bits_sign)
 			self.registers.append(reg)
 			for target in node.targets:
 				if isinstance(target, ast.Name):

migen/pytholite/reg.py

@@ -24,9 +24,9 @@ class LowerAbstractLoad(fhdl.NodeTransformer):
 			return node
 
 class ImplRegister:
-	def __init__(self, name, nbits):
+	def __init__(self, name, bits_sign):
 		self.name = name
-		self.storage = Signal(nbits, name=self.name)
+		self.storage = Signal(bits_sign, name=self.name)
 		self.source_encoding = {}
 		self.id_to_source = {}
 		self.finalized = False

migen/pytholite/transel.py

@@ -8,11 +8,20 @@ def bitslice(val, low, up=None):
 	return (val & mask) >> low
 
 class Register:
-	def __init__(self, nbits):
-		self._nbits = nbits
+	def __init__(self, bits_sign):
+		if isinstance(bits_sign, tuple):
+			self._nbits, self._signed = bits_sign
+		else:
+			self._nbits, self._signed = bits_sign, False
 		self._val = 0
 	
 	def _set_store(self, val):
+		if self._signed:
+			sbw = 2**(self._nbits - 1)
+			self._val = val & (sbw - 1)
+			if val & sbw:
+				self._val -= sbw
+		else:
 			self._val = val & (2**self._nbits - 1)
 	store = property(None, _set_store)