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targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)
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@ -72,7 +72,6 @@ class BaseSoC(SoCSDRAM):
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
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# EthernetSoC --------------------------------------------------------------------------------------
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