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interconnect/wishbone: Revert SRAM to Module, needs to be investigated.

This commit is contained in:
Florent Kermarrec 2023-10-27 15:24:57 +02:00
parent ff271b0b5f
commit d021564fca
1 changed files with 1 additions and 1 deletions
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litex/soc/interconnect/wishbone.py
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@ -392,7 +392,7 @@ class Converter(LiteXModule):
# Wishbone SRAM ------------------------------------------------------------------------------------ # Wishbone SRAM ------------------------------------------------------------------------------------
class SRAM(LiteXModule): class SRAM(Module): # FIXME: Switch to LiteXModule.
def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None): def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None):
if bus is None: if bus is None:
bus = Interface(data_width=32, address_width=32, addressing="word") bus = Interface(data_width=32, address_width=32, addressing="word")