cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.
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@ -29,31 +29,39 @@ class PicoRV32(Module):
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mem_wstrb = Signal(4)
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mem_wstrb = Signal(4)
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mem_rdata = Signal(32)
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mem_rdata = Signal(32)
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# PicoRV32 parameters. To create a new variant, modify this dictionary
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# and change the desired parameters.
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picorv32_params = {
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"p_ENABLE_COUNTERS" : 1,
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"p_ENABLE_COUNTERS64" : 1,
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# Changing REGS has no effect as on FPGAs, the registers are
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# implemented using a register file stored in DPRAM.
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"p_ENABLE_REGS_16_31" : 1,
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"p_ENABLE_REGS_DUALPORT" : 1,
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"p_LATCHED_MEM_RDATA" : 0,
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"p_TWO_STAGE_SHIFT" : 1,
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"p_TWO_CYCLE_COMPARE" : 0,
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"p_TWO_CYCLE_ALU" : 0,
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"p_CATCH_MISALIGN" : 1,
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"p_CATCH_ILLINSN" : 1,
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"p_ENABLE_PCPI" : 0,
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"p_ENABLE_MUL" : 1,
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"p_ENABLE_DIV" : 1,
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"p_ENABLE_FAST_MUL" : 0,
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"p_ENABLE_IRQ" : 1,
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"p_ENABLE_IRQ_QREGS" : 1,
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"p_ENABLE_IRQ_TIMER" : 1,
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"p_ENABLE_TRACE" : 0,
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"p_MASKED_IRQ" : 0x00000000,
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"p_LATCHED_IRQ" : 0xffffffff,
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"p_PROGADDR_RESET" : progaddr_reset,
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"p_PROGADDR_IRQ" : 0x00000010,
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"p_STACKADDR" : 0xffffffff
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}
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self.specials += Instance("picorv32",
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self.specials += Instance("picorv32",
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# parameters
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# parameters
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p_ENABLE_COUNTERS=1,
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**picorv32_params,
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p_ENABLE_COUNTERS64=1,
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p_ENABLE_REGS_16_31=1,
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p_ENABLE_REGS_DUALPORT=1,
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p_LATCHED_MEM_RDATA=0,
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p_TWO_STAGE_SHIFT=1,
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p_TWO_CYCLE_COMPARE=0,
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p_TWO_CYCLE_ALU=0,
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p_CATCH_MISALIGN=1,
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p_CATCH_ILLINSN=1,
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p_ENABLE_PCPI=0,
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p_ENABLE_MUL=1,
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p_ENABLE_DIV=1,
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p_ENABLE_FAST_MUL=0,
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p_ENABLE_IRQ=1,
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p_ENABLE_IRQ_QREGS=1,
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p_ENABLE_IRQ_TIMER=1,
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p_ENABLE_TRACE=0,
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p_MASKED_IRQ=0x00000000,
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p_LATCHED_IRQ=0xffffffff,
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p_PROGADDR_RESET=progaddr_reset,
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p_PROGADDR_IRQ=0x00000010,
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p_STACKADDR=0xffffffff,
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# clock / reset
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# clock / reset
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i_clk=ClockSignal(),
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i_clk=ClockSignal(),
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