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dvisampler: reset PLL at startup

This commit is contained in:
Sebastien Bourdeauducq 2013-09-08 12:55:26 +02:00
parent 52be94f060
commit d0edb7e2b8
1 changed files with 1 additions and 1 deletions
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2
milkymist/dvisampler/clocking.py
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@ -4,7 +4,7 @@ from migen.bank.description import *
class Clocking(Module, AutoCSR): class Clocking(Module, AutoCSR):
def __init__(self, pads): def __init__(self, pads):
self._r_pll_reset = CSRStorage() self._r_pll_reset = CSRStorage(reset=1)
self._r_locked = CSRStatus() self._r_locked = CSRStatus()
self.locked = Signal() self.locked = Signal()