dvisampler: reset PLL at startup

2013-09-08 12:55:26 +02:00 · 2013-09-08 12:55:26 +02:00 · d0edb7e2b8
parent 52be94f060
commit d0edb7e2b8
1 changed files with 1 additions and 1 deletions
--- a/milkymist/dvisampler/clocking.py
+++ b/milkymist/dvisampler/clocking.py
@ -4,7 +4,7 @@ from migen.bank.description import *

 class Clocking(Module, AutoCSR):
 	def __init__(self, pads):
-		self._r_pll_reset = CSRStorage()
+		self._r_pll_reset = CSRStorage(reset=1)
 		self._r_locked = CSRStatus()

 		self.locked = Signal()