mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
cva6: Adding missing common_cells sources
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
parent
d90f8809b4
commit
d137416739
1 changed files with 10 additions and 0 deletions
|
@ -77,6 +77,16 @@ ${CVA6_REPO_DIR}/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv
|
|||
${CVA6_REPO_DIR}/corev_apu/clint/clint.sv
|
||||
${CVA6_REPO_DIR}/corev_apu/clint/axi_lite_interface.sv
|
||||
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/stream_register.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/counter.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/delta_counter.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/spill_register.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/spill_register_flushable.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/onehot_to_bin.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/id_queue.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/addr_decode.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/cdc_2phase.sv
|
||||
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/deprecated/fifo_v1.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/deprecated/fifo_v2.sv
|
||||
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
|
||||
|
|
Loading…
Reference in a new issue