cpu/mor1kx: Adding verilog include directory.

2018-10-03 21:57:24 -07:00 · 2018-10-03 21:57:24 -07:00 · d13ac3b3d5
parent dc7cd75757
commit d13ac3b3d5
1 changed files with 1 additions and 0 deletions
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@ -122,3 +122,4 @@ class MOR1KX(Module):
            os.path.abspath(os.path.dirname(__file__)),
            "verilog", "rtl", "verilog")
        platform.add_source_dir(vdir)
+        platform.add_verilog_include_path(vdir)