add sim: tb_TriggerCsr.py

migScope/__init__.py

@@ -196,16 +196,15 @@ class Trigger:
 					access_bus=WRITE_ONLY, access_dev=READ_ONLY))
 			elif isinstance(self.ports[i],RangeDetector):
 				setattr(self,"_range_reg%d"%i,RegisterField("rst", 2*self.trig_width, reset=0,
-					access_bus=WRITE_ONLY, access_dev=READ_ONLY))
-					
-		self._sum_reg = RegisterField("_sum_reg", 17, reset=0,access_bus=WRITE_ONLY, access_dev=READ_ONLY)
+					access_bus=WRITE_ONLY, access_dev=READ_ONLY))		
+		self._sum_reg = RegisterField("_sum_reg", 32, reset=0,access_bus=WRITE_ONLY, access_dev=READ_ONLY)
 		
 		regs = []
 		objects = self.__dict__
-		for object in objects:
+		for object in sorted(objects):
 			if "_reg" in object:
+				print(object)
 				regs.append(objects[object])
-		regs.append(self._sum_reg)
 		self.bank = csrgen.Bank(regs,address=address)
 		
 	def get_fragment(self):
@@ -215,7 +214,6 @@ class Trigger:
 		comb+= [port.i.eq(self.in_trig) for port in self.ports]
 		
 		# Connect output of trig elements to sum
-		# Todo : Add sum tree to have more that 4 inputs
 		comb+= [self._sum.i[j].eq(self.ports[j].o) for j in range(len(self.ports))]
 		
 		# Connect sum ouput to hit
@@ -241,8 +239,9 @@ class Trigger:
 				comb += [self.ports[i].high.eq(getattr(self,"_range_reg%d"%i).field.r[1*self.trig_width:2*self.trig_width])]
 				
 		comb += [
-			self._sum.prog_dat.eq(self._sum_reg.field.r[0:16]),
-			self._sum.prog.eq(self._sum_reg.field.r[16]),
+			self._sum.prog_adr.eq(self._sum_reg.field.r[0:16]),
+			self._sum.prog_dat.eq(self._sum_reg.field.r[16]),
+			self._sum.prog.eq(self._sum_reg.field.r[17])
 			]
 		return frag + Fragment(comb=comb, sync=sync)
 

sim/tb_TriggerCsr.py

@@ -0,0 +1,96 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.sim.generic import Simulator, PureSimulable, TopLevel
+from migen.sim.icarus import Runner
+from migen.bus.transactions import *
+
+import sys
+sys.path.append("../")
+import migScope
+
+def term_prog(off, dat):
+	for i in range(4):
+		yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
+
+
+def sum_prog(off, addr, dat):
+	we = 2
+	yield TWrite(off+3, addr%0xFF)
+	yield TWrite(off+2, (addr>>8)%0xFF)
+	yield TWrite(off+1, we+dat)
+	yield TWrite(off+0, 0)
+	for i in range(4):
+		TWrite(off+i,0)
+
+
+csr_done = False
+
+def csr_transactions():
+
+	term_trans = []
+	term_trans += [term_prog(0x04  ,0xDEADBEEF)]
+	term_trans += [term_prog(0x08  ,0xCAFEFADE)]
+	term_trans += [term_prog(0x0C  ,0xDEADBEEF)]
+	term_trans += [term_prog(0x10  ,0xCAFEFADE)]
+	for t in term_trans:
+		for r in t:
+			yield r
+
+	sum_trans = []
+	sum_trans += [sum_prog(0x00,i,1) for i in range(8)]
+	sum_trans += [sum_prog(0x00,i,0) for i in range(8)]
+	for t in sum_trans:
+		for r in t:
+			yield r
+	
+	global csr_done
+	csr_done = True
+	
+	for t in range(100):
+		yield None
+
+
+def main():
+	# Csr Master
+	csr_master0 = csr.Initiator(csr_transactions())
+
+	# Trigger
+	term0 = migScope.Term(32)
+	term1 = migScope.Term(32)
+	term2 = migScope.Term(32)
+	term3 = migScope.Term(32)
+	trigger0 = migScope.Trigger(0, 32, 64, [term0, term1, term2, term3])
+	
+	# Csr Interconnect
+	csrcon0 = csr.Interconnect(csr_master0.bus, 
+			[
+				trigger0.bank.interface
+			])
+
+	# Term Test
+	def term_stimuli(s):
+		if csr_done:
+			s.wr(term0.i,0xDEADBEEF)
+			s.wr(term1.i,0xCAFEFADE)
+			s.wr(term2.i,0xDEADBEEF)
+			s.wr(term3.i,0xCAFEFADE)
+
+	
+	# Simulation
+	def end_simulation(s):
+		s.interrupt = csr_master0.done
+
+	fragment = autofragment.from_local()
+	fragment += Fragment(sim=[end_simulation])
+	fragment += Fragment(sim=[term_stimuli])
+	sim = Simulator(fragment, Runner(),TopLevel("myvcd"))
+	sim.run(2000)
+
+main()
+input()
+
+
+
+
+

sim/tb_migScopeCsr.py

@@ -1,60 +0,0 @@
-from migen.fhdl.structure import *
-from migen.fhdl import verilog, autofragment
-from migen.bus import csr
-from migen.sim.generic import Simulator, PureSimulable, TopLevel
-from migen.sim.icarus import Runner
-from migen.bus.transactions import *
-
-from random import Random
-
-import sys
-sys.path.append("../")
-import migScope
-
-
-def csr_transactions():
-	prng = Random(92837)
-
-	# Write to the first addresses.
-	for x in range(10):
-		t = TWrite(x, 2*x)
-		yield t
-		print("Wrote in " + str(t.latency) + " cycle(s)")
-		# Insert some dead cycles to simulate bus inactivity.
-		for delay in range(prng.randrange(0, 3)):
-			yield None
-
-	# Read from the first addresses.
-	for x in range(10):
-		t = TRead(x)
-		yield t
-		print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
-		for delay in range(prng.randrange(0, 3)):
-			yield None
-
-
-
-def main():
-	# Csr Master
-	csr_master0 = csr.Initiator(csr_transactions())
-
-	term0 = migScope.Term(32)
-
-	trigger0 = migScope.Trigger(0,32,64,[term0])
-	csrcon0 = csr.Interconnect(csr_master0.bus, 
-			[
-				trigger0.bank.interface
-			])
-	def end_simulation(s):
-			s.interrupt = csr_master0.done
-
-	fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(),TopLevel("myvcd"))
-	sim.run(20)
-
-main()
-
-
-
-
-

top.py

@@ -39,7 +39,7 @@ import spi2Csr
 #
 #Test Sum
 #
-#sum = migScope.Sum(4,pipe=True)
+#sum = migScope.Sum(4,pipe=False)
 #v = verilog.convert(sum.get_fragment())
 #print(v)
 
@@ -74,21 +74,21 @@ import spi2Csr
 #
 #Test Trigger
 #
-#term0 = migScope.Term(32)
-#term1 = migScope.RangeDetector(32)
-#term2 = migScope.EdgeDetector(32)
-#term3 = migScope.Term(32)
+term0 = migScope.Term(32)
+term1 = migScope.RangeDetector(32)
+term2 = migScope.EdgeDetector(32)
+term3 = migScope.Term(32)
 
-#trigger0 = migScope.Trigger(0,32,64,[term0, term1, term2, term3])
-#recorder0 = migScope.Recorder(0,32,1024)
-#v = verilog.convert(trigger0.get_fragment()+recorder0.get_fragment())
-#print(v)
+trigger0 = migScope.Trigger(0,32,64,[term0, term1, term2, term3])
+recorder0 = migScope.Recorder(0,32,1024)
+v = verilog.convert(trigger0.get_fragment()+recorder0.get_fragment())
+print(v)
 
 #
 #Test spi2Csr
 #
-spi2csr0 = spi2Csr.Spi2Csr(16,8)
-v = verilog.convert(spi2csr0.get_fragment())
-print(v)
+#spi2csr0 = spi2Csr.Spi2Csr(16,8)
+#v = verilog.convert(spi2csr0.get_fragment())
+#print(v)