61 lines
1.3 KiB
Python
61 lines
1.3 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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from random import Random
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import sys
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sys.path.append("../")
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import migScope
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def csr_transactions():
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prng = Random(92837)
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# Write to the first addresses.
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for x in range(10):
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t = TWrite(x, 2*x)
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yield t
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print("Wrote in " + str(t.latency) + " cycle(s)")
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# Insert some dead cycles to simulate bus inactivity.
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Read from the first addresses.
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for x in range(10):
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t = TRead(x)
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yield t
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print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
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for delay in range(prng.randrange(0, 3)):
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yield None
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def main():
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# Csr Master
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csr_master0 = csr.Initiator(csr_transactions())
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term0 = migScope.Term(32)
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trigger0 = migScope.Trigger(0,32,64,[term0])
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csrcon0 = csr.Interconnect(csr_master0.bus,
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[
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trigger0.bank.interface
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])
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def end_simulation(s):
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s.interrupt = csr_master0.done
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fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(),TopLevel("myvcd"))
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sim.run(20)
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main()
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